\begin{abstract}
Recently, the research of floating-body DRAM~(FBDRAM) has attracted
more attention. Compared to the traditional DRAM technology, FBDRAM
has many advantages, such as high density, fast access speed, long
retention time, etc. More important, FBDRAM is totally compatible with
CMOS technology, which makes it more competitive than other emerging
memory technologies to be employed as on-chip memory. However, the
parameter variations among different cells have become the obstacle of
adopting FBDRAM design. In this work, we build a model FBDRAM caches
with the consideration of process variations.  With this model, we
explore the L2 cache design using FBDRAM and compare it with
traditional SRAM/eDRAM caches, in respect of performance, power
consumption, and reliability. In addition, we present mechanisms to
mitigate the impact of process variations on FBDRAM caches.
\end{abstract}
